What are the three types of AXI protocols?
AXI has been introduced in 2003 with the AMBA3 specification. In 2010, a new revision of AMBA, AMBA4, defined the AXI4, AXI4-Lite and AXI4-Stream protocol.
What is the AXI protocol?
The AXI is a point to point interconnect that designed for high performance, high speed microcontroller systems. The AXI protocol is based on a point to point interconnect to avoid bus sharing and therefore allow higher bandwidth and lower latency. AXI is arguably the most popular of all AMBA interface interconnect.
How many channels are there in AXI protocol?
five channels
The AXI protocol defines five channels: three for write signals, and two for read signals.
What are the advantages of AXI protocol?
Advantages of the AMBA 3 AXI protocol include:
- Independently acknowledged address and data channels.
- Out-of-order completion of bursts.
- Exclusive access (atomic transaction)
- System level cache support.
- Access security support.
- Unaligned address & byte strobe.
- Static burst, which allows bursts to FIFO memory.
- Low power mode.
Where is AXI protocol used?
The protocol used by many SoC today is AXI, or Advanced eXtensible Interface, and is part of the ARM Advanced Microcontroller Bus Architecture (AMBA) specification. It is especially prevalent in Xilinx’s Zynq devices, providing the interface between the processing system and programmable logic sections of the chip.
How does AXI interconnect work?
The AXI Interconnect IP connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specifications from ARM®, including the AXI4-Lite control register interface subset.
What is the use of AXI interface?
AXI interconnects allow multiple masters and/or multiple slaves to interface with each other. The AXI specification defines the interface between a master and slave, a master and interconnect, and a slave and interconnect.
How does AXI ID work?
The AXI protocol defines an ID signals bus for each channel. Marking each transaction with an ID gives the possibility to complete transactions out of order. This means that transactions to faster memory regions can complete without waiting for earlier transactions to slower memory regions.
What is locked access in AXI?
The AXI protocol specifies that, when a locked transaction occurs, the master must follow the locked transaction with an unlocked transaction to remove the lock of the interconnect. The locked sequence is not complete until the end of the locking transaction.
What is AXI memory?
The AXI slave interface is a memory-mapped interface to an on-chip memory block. This interface is intended to be controlled by an AXI or Avalon-MM master interface, which can write to and read from the memory block. Parameters specify the AXI ID signal widths, the slave address width, and the data width.
What is narrow transfer in AXI?
When a master generates a transfer that is narrower than its data bus, the address and control information determine which byte lanes the transfer uses. In incrementing or wrapping bursts, different byte lanes transfer the data on each beat of the burst.
What is beat and burst length in AXI?
The AXI3 protocol allows up to 16 beats in any burst transaction, whereas the AXI4 protocol allows for up to 256 beats in an INCR type burst transaction.
What is aligned and unaligned address in AXI?
32 bit value two lower address bits need to be zero to be aligned. A 32 bit value at 0x1000 is aligned but 0x1001, 0x1002, 0x1003 would all be unaligned. Memories are generally not 8 bits wide from an interface perspective as well as a geometry, depends on what kind of memory or where.
Why there is no read response channel in AXI?
The reason why we do not have a separate response channel for read data is the read data always originate from the information producer. This producer already knows if the read request from the consumer produced ok/not-ok response as soon as it receives the read request.
What is data interleaving in AXI?
Write data interleaving enables a slave interface to accept interleaved write data with different AWID values. The slave declares a write data interleaving depth that indicates if the interface can accept interleaved write data from sources with different AWID values.
What is wrap boundary in AXI?
The wrap boundary is the size of each transfer in the burst multiplied by the total number of transfers in the burst. Two restrictions apply to wrapping bursts: the start address must be aligned to the size of the transfer. the length of the burst must be 2, 4, 8, or 16.
What is write strobe in AXI?
The AXI write strobe signal is used to indicate which bytes of the write data bus are valid for each transfer of data. By using them you can perform sparse data transfers. For example; when performing a write transaction on a 32 bit data bus, you will have a WSTRB signal that’s 4 bits wide.
What is the fixed burst type in AXI?
FIXED burst: In a fixed burst-type, single address is used for storing data that is frequently used by the slave similar to a FIFO for every transfer in the burst. This type of burst enables repeated accesses to the same location.
What is the relationship between AXI channels?
Each AXI channel transfers information in only one direction, and the architecture does not require any fixed relationship between the channels. This means a register stage can be inserted at almost any point in any channel, at the cost of an additional cycle of latency. What is control information?
What is the minimum and maximum bus width supported in axi?
So the first transaction is an outstanding transaction. AXI supports multiple outstanding transactions so an AXI master doesn’t have to wait for a transaction to complete to initiate a new one. So the performance is boosted. What is the minimum and maximum data bus width supported in AXI? The data bus width as per spec can be 8,16,32…,1024 bits.
Can AXI slave send read/write addresses from AXI master side?
No. Addresses (read/write) are generated only from the AXI Master side only. It is the READ data and write response channels that are owned by AXI slave. The slave will only be sending READ Data, READ response, WRITE Responses.
What is upper and lower byte Lane in axi?
The byte lane of the highest addressed byte of a transfer is the upper byte lane and the lowest addressed byte of a transfer is the lower byte lane. AXLEN = 4 then burst length? Burst_length = AxLEN+1 so 5. AXI supports for burst length for the incr burst type is 1-256 bytes and for fixed, wrap is 1-16 bytes. (True/False) True.